module frequency_divisio_10Hz(
	input clk_50M,
	input rst_n,
	output reg clk_10Hz
);

	reg[23:0] counter;

	always @(posedge clk_50M or negedge rst_n) begin
		
		if(rst_n == 1'b0) begin
			counter <= 24'd0;
			clk_10Hz <= 1'b0;
		end
		else begin
			if(counter == 24'd2_499_999) begin
				counter <= 24'd0;
				clk_10Hz <= ~clk_10Hz;
			end
			else begin
				counter <= counter + 1;
			end
		end
		
	end
	
endmodule
